Current main topic notes (includes mini-projects, common circuits and common code snippits etc.)
(+) 6010 PC Parallel port pin out
(+) 6020 MIC in Oscilloscope
(+) 6020 MIC in osc
(-) 8010 555 timer operation
Image, left, is how the 555 Timer chip is typically shown in 'block diagram' form.
Whilst it retains the correct pin positioning, it's virtually impossible to understand the actual operation 'at a glance'.
To understand "how it works", the diagram has to be 'un-wound' ...
How the 555 timer works
Image, left, is the 555 Timer block diagram 'un-wound' for easy understanding.
Internally, the original 555 essentially consist a chain of three resistors (originally, 5k, hence '555'), two comparators, and a flip-flop (driving the output circuit and an NPN 'discharge' transistor).
The 3 resistor chain divides the voltage between pin8, Vcc, and pin1, Gnd, into 1/3rds. When pin2, Trigger, is below 1/3 Vcc, the flip-flop is 'set' and pin3, Output, is driven Hi (whilst pin7, Discharge, is 'floating' (off, or 'no connect') ) When pin6, Threshold, exceeds 2/3 Vcc, the flip-flop is 'reset' and pin3, Output, is driven Lo (as is pin7, Discharge) Pin5, Control, is used to change the 2/3 point (if unused it is typically wired with 10nF to Gnd) The final pin4, Reset, when Lo (typ. 0v7 or less) resets the flip-flop (so o/p Lo, Discharge driven to Gnd), irrespective of the state of the other control pins. When unused, it is tied direct to Vcc. Vcc is typically 4.5v-14v and o/p pin 3 can typically drive or sink 200mA ! In monostable mode, pin6 & pin7 are wired in common to R1 Vcc, C1 Gnd. When Trigger falls below 1/3V, the flip-flop is set and the o/p goes Hi. Since Discharge is 'off', C1 starts to charge via R1. After 1.1 * R1 * C1 seconds, 2/3V is reached and the o/p goes Lo again (and Discharge pulls C1 to Gnd ready for the next trigger) NOTE that multiple 'Triggers' during the 'charge up' period have no effect on the timing. The first Trigger sets the flip-flop and the timer starts - the flip-flop will only reset when pin6 reaches 2/3V irrespective of any further Triggers during C1*R1 charging
This note last modified: 3rd Feb 2018 05:35.