**The R-2R binary DAC**
To calculate the contribution of each 'bit' to the R-2R chain, you can use "Thevenin's theorem" to reduce the circuit to single voltage source with series resistor. If the 'top of the chain' Vtop is feeding an Op-Amp wired as a 'voltage follower' (so Vtop to Op-Amp +ve, Op-Amp -ve connected direct to Op-Amp o/p), the current drawn at Vtop will be 'zero' and the circuit is solved.
However in the 'real world' the TTL drive voltages are not 0v and 5v = 0v3v and 3v3 is typical for TTL (shown above), but the PIC generates 0v6 and 4v3, and this is ONLY if the current flowing into (or out of) the PIC pin is within specification (typ. less than 20mA).
The obvious thing to do is simulate the circuit using SPICE with your actual PIC Hi/Lo output voltages (usually Vdd-0.7 and 0v6). This will let you calculate the expected current source/sink values to ensure they stay within the PIC limits = you will need to check individual pin currents, the 'PORT' current limit and the overall chip limit. If you exceed the specification sheet limits the pin voltages will no longer meet the values expected (plus excessive current is the fastest way to excessive heat and chip failure)
## SPICE simulation

LT-spice (free) is the 'de-facto standard' and you can find the LTspice IV (free) download here. The package is only 15.3Mb (which, I guess, tells you something about it's age :-) ).
There is plenty of documentation 'on-line', however I suggest reading the a 'step by step' guide (found on the SPICE Wikipedia page)
## Ternary logic

Binary gives you 2^n states, ternary 3^n. This makes a real difference very quickly - 3 binary bits (2^3) is only 8 states, whist 3 ternary (3^3) is 27 ! To get a 64 state DAC we need 6 binary bits, whilst 4 ternary 'tets' gives us 81 !

### How it works

PIC pins have 3 distinct states = output Lo (typ 0.6v), output Hi (typ 4.3v) and input 'nothing' (high impedance). To convert the 'nothing' into a 'half'** level voltage, a pair of 'low value' resistors (low value compared to the 'chain' resistors) are typically added, one to 5v the other to Gnd

##### Pin Lo is 0.6 and Hi is 4.3v, so Vhalf = (0.6+4.3/)/2 = 2.45v (so within 2%), however that's not quite the end of the story, since at high (20mA) loads the pin output voltage may not reach 4.3v (nor go as low as .6v) and (as usual) actual device operation is likely to differ from the data sheet (which shows only the min Hi and max Lo).

Unfortunately there seems to be no data on 'real world' PIC pin o/p voltages V's current, so I started with 'data sheet' values (using LTspice) and then measured actual performance with a 'breadboard' of the design

When the PIC pin is used as an output, the divider resistors will dominate the current draw. If we want to keep within 20mA**, Rdivider = 5/.02 = 250 ohms, or nearest E24 (5%) = 270 ohms (although we are using 5% resistors that's the 'absolute value' accuracy - in any 'random' batch you should be able to find 2 resistors making a 'matched pair' (i.e. correct ratio) to within the accuracy of your multimeter (typ 4 digits i.e. .1%) and that's all we need).

##### **The PIC has both a pin limit (20/25mA) and a 'total PORT' limit (typically 100mA). So you can build a 5 pin DAC at 20mA per pin, but a 6 pin DAC means reducing the current from each to 100/6 = 16mA ..

Of course when driving (or sinking) 20mA the pin output voltage will won't be 4.3v (or .6v) !

Next we consider the R-nR 'ladder'. For ternary 'chain' the ratios need to be 3R/4R (rather than R/2R). Since the 'chain' resistors must be high enough to avoid impacting the 'divider' resistor effect, the 'obvious' choice is 75k and 100k.

##### A 4 pin ternary DAC means a 400k 'chain' resistance. A typical Op-Amp (LM741) has a typical input resistance of 2M Ohm, which is not insignificant compared to a 4 x 100k chain resistance of 0.4M ohm !

Reducing the 'chain' resistor values will reduce the effect of Op Amp input resistance however this means increases the effect of the voltage divider resistors. So we have an accuracy trade-off = to which the only answer is the simulate (LTspice) the circuit and then breadboard it.

### Hybrid approach

LTspice suggests that a 3 pin 'ternary' DAC (so 3x3x3 = 27 levels) 'works' well, however above this the 'half voltage' divider of a 4th ternary pin (needed for 'ternary' operation) overwhelms the lower level voltages of the 3 lower pins to the point where steps are 'reversed' when the high pin is switched.

The 'trick' is to run the 4th (and 5th) bit in 'binary' mode. This allows 5 pins to deliver 27x2x2 = 108 levels, whilst a 'pure binary' 5 bits would deliver only 32 levels !