Conversion from 7 bit binary to hybrid control (3 ternary + 2 binary) The 3 hybrid ternary bits require 2 control bits each, i.e. 6 control bits for all 3. The 'top' two hybrid bits are binary, so that's 2 more control bits = 8 bits in total (lucky, that :-) ) There are two basic ways of converting a 7 bit 'count' into the 'hybrid' control byte = by calculation or by LUT (Look-Up-Table) A LUT will be faster (and the output control 'bit definitions' can be whatever you like) but, on the other hand, a calculation may deliver a solution in fewer total instructions, which is vital on the low end devices (eg. the 16F54 which only has 512 instruction space !) Control LUT A hybrid DAC built with 3 ternary + 2 binary control bits has 108 distinct states, so the LUT will have 108 entries (one for each control byte), plus a few extra 'steering' instructions. The advantages of a LUT is that the 'conversion' doesn't have to be 'linear' = for example you could code a (1/4) sine-wave function (for AC waveform generation) or a "+/-" offset about a middle value. If the hybrid DAC output is controlling a servo motor, and the +/- value is derived from a speed feedback circuit, you might want the LUT to code a (fast) 'speed up' ramp (from zero) and a 'gradual change' about the 'mid point' ... which would be 'offset' from the 'count 50' code. For example, 'count 128' (0x80 = top bit set) could be defined as the 'mid point', with (say) +/- 32 counts either side (so 0x60 - 0xA0, 64 values) for 'mid speed control', leaving 108-64 = 40 counts for 'speed up from zero to (low) mid point' The observant will note that the 'speed up' count runs from 0x00 - 0x5F, which is 96 counts. Since we want a 'fast speed up' (and to avoid wasting too many extra LUT locations), counts of less than 0x60 would be 'divided by 4' (or even 8) before being used as a look-up address, so the 'extra' locations for speed-up will be reduced to 24 (or 12), resulting a 64+24 = 88 (76) entry table. Defining the control byte One problem with all DAC outputs is how to prevent 'glitches' when the 'drive' bit values are changed. This is especially difficult with a tri-state system (because the 'set tri-state (TRIS)' command and 'set PORT (output latch) bits' commands both require the control bits to be in the Accumulator = so there will be at least a 2 instruction delay between setting tri-state and setting bits. To minimise 'glitches', the output bits could be changed 'one step at a time' in such a way that there are no 'big jumps' in the output value - although that means keeping a copy of the previous settings (as reading the PORT gets the pins 'state' (not the output latch settings), and reading TRIS gets 0's) On the other hand, in many applications, a 'glitch' that is 'corrected' after 2 CLK's of a 1 MIPS CPU may not be noticeable Of course things are a little simpler if only 4 (3 ternary + 1 binary) bits are being used with a 16F5x device (all the 16F5x devices have a 4 bit 'PORT A', which means the 'control' byte can can be formed of 4 TRIS bits + 4 PORT bits = grouping into 4 bits means the SWAPF command can be used to 'switch nibbles' between TRIS A and PORT A).