Current main topic notes (includes mini-projects, common circuits and common code snippits etc.)
(+) 02 Avoiding Jitter
(+) 02 RAM disks
(+) 0300 Jitter tests
(-) 07 The nonsense of RISC
The nonsense of RISC Reduced Instruction Set Computer is based on the simplistic idea that a simple CPU chip can be made to execute simple instructions faster .. .. and 'in general' this is true = a RISC chip typically executes one instruction per clock cycle whilst a CISC (Complex Instruction Set Computer) chip can take 10-20 clock cycles to execute a single instruction. To achieve the same 'end result', the RISC chip 'only' needs 4 or 5 times as many instructions - so 'in theory' it might seem that a RISC would be up to 4 times faster than a CISC chip. But this ignores the fact that the 'bottle-neck' is NOT how fast the CPU can execute an instruction (i.e. it's not the CPU clock speed that limits how fast the software runs) but rather the speed with which the instructions can be fetched from RAM. This is because RAM is, has been, and always will be, much 'slower' than the CPU = first the CPU has to issue an 'address' to the RAM, the RAM then has to find the data, finally the CPU has to 'accept' the data. So, even in the 'perfect world', with all the RAM on the same chip as the CPU circuits (so there are no speed limits imposed by external circuit board 'tracks' ), the RAM will be 3-4 times slower than the CPU clock. On a typical motherboard, the RAM is 10-20 slower than the CPU. This fact was known even in the 1980's, when 'microprocessor' (CISC) CPU designs were already incorporating 'pipe-lines' and mainframes were already using something called 'cache memory' and IBM was designing it's PowerPC RISC chip. In fact, the typical CISC CPU with a clock running at about 10 times the 'raw' RAM speed, was well 'matched' to the RAM speed (when the CPU was taking 10 or so CPU cycles to 'execute' each instruction fetched) i.e. it would spend very little time 'waiting' for the next instruction. However RISC, with the ability to execute one instruction per clock cycle, had a problem. If you ran the chip at 10x the RAM speed, it would be sitting idle 90% of the time, just waiting for it's next instruction - and what's more, it would then need fetch and execute another 3 or 4 instructions just to perform the same function as the CISC chip did with 1 instruction. One way to 'address' this 'problem' was to increase the RAM 'width' (i.e. fetch multiple instructions at once). But this required RAM that was 4 or 5 instructions 'wide' just to 'match' CISC speed .. and wider RAM cost more (as did the higher pin counts needed to get the data into the RISC chip). Even worse, the '4 instruction wide' RAM could be used with a CISC chip - which could then be run 4 times faster. The only real way to 'beat' CISC was to use ultra-high-speed RAM i.e. RAM on the same die as the CPU. Before IC transistor counts started to take off, only a very limited amount of RAM could be added to the chip (although a RISC chip would could use the space saved by not implementing complicated instructions for this) as using lots of high speed external RAM would be prohibitively expensive. So the main RAM would be 'standard speed' with as much on-board cache as possible would be added to the design (to get the speed up). This then, eliminated the 'cost advantage' that a RISC chip would bring by using a smaller chip 'die size'. If anything, RISC designs needed bigger die sizes than CISC. Indeed, in the days when all RAM was expensive, a CPU design that needed 4 or 5 times as much RAM to run the same software as a competitors should have been an obvious 'non-starter' in the consumer market from the start. However, as IC transistor counts increased, CISC CPU's could make use the same high-speed 'cache' tricks - and since they started with a 4-5 times advantage over the RISC, RISC would always be 'running to catch up'. RISC, then, was 'nonsense' from day 1 = it made sense only to IBM (because the PowerPC instruction set was based on a 1960's mainframe design, which (of course) had to be extremely simple because it was implemented in discrete logic gates) - and IBM was, of course, a company to whom 'cost was no object' (as were Apple Mac. customers, the users of the PowerPC chip). By the time the PowerPC became available (about 1991), the rest of the world was running on Intel 80386 and 80486 CISC chips - and the Pentium was already being designed. Rather than 'reduce' the Instruction set, as the number of transistors in (and the speed of) Integrated Circuits (ICs) doubled every 18 months or so, it made (a lot) more sense to increase the instruction set by adding more and more CPU instructions that were more and more complicated and thus cut down on the number of RAM fetches needed 'per function'. This was the approach followed by Intel = and this is way Intel CPU chips now 'rule the world' (even the Apple 'Mac.' now uses an Intel CPU).
This note last modified: 15th Apr 2017 04:59.